1. Field of the Invention
This invention relates generally to a clock generator and more particularly to a write clock generator used for a time base corrector (TBC) which is provided in the reproducing system of a video tape recorder (VTR).
2. Description of the Prior Art
Generally, a time base corrector is provided in the reproducing system of a professional VTR and so on in order to remove a jitter in a reproduced video signal or the like. This time base corrector requires a write clock generator for generating a write clock pulse which is capable of accurately following the jitter of the reproduced video signal and which is in phase with a color burst signal.
FIG. 1 is a block diagram showing an example of such prior art write clock pulse generator 10 for use with the time base corrector which is disclosed more in detail in, for example, U.S. Pat. No. 4,165,524 (by the same assignee).
Referring to FIG. 1, a reproduced video signal Sv applied to a terminal 1 is supplied to a synchronous separating circuit 2 in which a horizontal synchronizing signal P.sub.H is separated from the reproduced video signal Sv. This horizontal synchronizing signal P.sub.H is supplied to a PLL (phase locked loop) circuit 3 which forms a clock CK.sub.1 of the frequency nf.sub.H (n is an integer and f.sub.H is a horizontal frequency) following the frequency fluctuation of the horizontal synchronizing signal P.sub.H. In this example, n is selected to be 910 for the NTSC system and 1135 for the PAL system, respectively.
The reproduced video signal Sv is further supplied to a color burst separating circuit 4 in which a color burst signal S.sub.B is separated from the reproduced video signal Sv. This color burst signal S.sub.B is supplied to an APC (automatic phase control) circuit 5 which synchronizes the phase of the clock CK.sub.1 supplied thereto. Thus, at an output terminal 6 led out from the APC circuit 5, there is developed a write clock CK.sub.W synchronized in phase with the color burst signal S.sub.B and the frequency of which is the same as that of the clock CK.sub.1.
Though not shown, the write clock CK.sub.W is used as a sampling clock for analog-to-digital converting the reproduced video signal Sv and also as a write clock for a digital memory.
By the way, when the clock generating circuit 10 is arranged as described above, the APC circuit 5 for phase-synchronization generally includes a vast number of circuit elements and in which an analog signal processing system and a digital signal processing system exist therein in a mixed state so that this clock generating circuit 10 is not suitable for being formed as an IC (integrated circuit). Further, this prior art clock generating circuit 10 has the analog signal processing system so that its temperature characteristic is poor and that its operation is not stabilized.